The present invention generally relates to memory devices, and, more particularly, to a read-only memory (ROM) device with a multi-bit line bit cell.
Memory devices store information such as instructions and data. Non-volatile memory devices retain the stored information even when its power supply is interrupted and hence provide a permanent storage of information. Examples of non-volatile memory devices are ROM, erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM) devices. A ROM generally stores firmware and boot code. A mask ROM stores information during the fabrication process. The ROM includes a memory array, an address decoder, a pre-charging unit, a sensing unit, and a column multiplexing unit. The memory array also includes memory cells, bit lines, and word lines.
When a processor connected to the ROM performs a memory read operation, the processor generates first and second binary addresses corresponding to word and bit lines, respectively, to read a memory cell in the memory array. The address decoder receives and decodes the addresses to select the word and bit lines. The address decoder selects a bit line by way of the column multiplexing unit. The column multiplexing unit is connected to the pre-charging and sensing units. During the read operation, the column multiplexing unit selects the pre-charging unit for a predefined time interval. The pre-charging unit charges the bit line to a predefined voltage level and then the column multiplexing unit selects the sensing unit. The sensing unit senses the predefined voltage level of the bit line and determines the data value stored in the memory cell based on the sensed voltage level.
FIG. 1 is a schematic circuit diagram of a conventional ROM array 100. The ROM array 100 is a 2×2 array and includes first through fourth transistors 102a-102d (collectively referred to as transistors 102), first and second bit lines 104a and 104b (collectively referred to as bit lines 104), first and second word lines 106a and 106b (collectively referred to as word lines 106), and first and second ground lines 108a and 108b (collectively referred to as ground lines 108). The transistors 102 form first through fourth memory cells M1, M2, M3, and M4, respectively, and store first through fourth data values, respectively.
Each transistor 102 has a gate terminal, and first and second diffusion terminals. The gate terminals of the first and second transistors 102a and 102b are connected to the first word line 106a and the gate terminals of the third and fourth transistors 102c and 102d are connected to the second word line 106b. The first diffusion terminals of the first and second transistors 102a and 102b are connected to the first ground line 108a, and the second diffusion terminals are connected to the first and second bit lines 104a and 104b for storing the first and second data values in the first and second memory cells M1 and M2. The first diffusion terminal of the third transistor 102c is floating and the second diffusion terminal thereof is connected to the first bit line 104a for storing the third data value in the third memory cell M3. The first diffusion terminal of the fourth transistor 102d is connected to the second ground line 108b and the second diffusion terminal thereof is connected to the second bit line 104b for storing the fourth data value in the fourth memory cell M4. In an example, the first, second, and fourth data values correspond to logic zero and the third data value corresponds to logic one. In another example, the first, second, and fourth data values correspond to logic one and the third data value corresponds to logic zero. The first and second diffusion terminals may be either source or drain terminals.
FIG. 2 is a schematic layout diagram of a conventional ROM array 200. The ROM array 200 is a 2×2 ROM array and represents the ROM array 100 of FIG. 1. The ROM array 200 includes first and second active regions 202a and 202b (collectively referred to as active regions 202) that are formed on a semiconductor substrate 204. First and second gate electrode strips 206a and 206b (collectively referred to as gate electrode strips 206) are formed over the active regions 202. First through eighth metal strips 208a-208h (collectively referred to as metal strips 208) are formed over the active regions 202 and the gate electrode strips 206 by way of and first through seventh contacts 210a-210g (collectively referred to as contacts 210). The first through sixth metal strips 208a-208f are metal 1 metal strips and the seventh and eighth metal strips 208g and 208h are metal 2 metal strips. The first active region 202a includes first through third diffusion regions of which the first and third diffusion regions are source regions and the second diffusion region is a drain region. The second active region 202b includes fourth through sixth diffusion regions of which the fourth and sixth diffusion regions are source regions and the fifth diffusion region is a drain region. The gate electrode strips 206 are polysilicon strips.
The first and second diffusion regions and the first gate electrode strip 206a form a first transistor T1. The fourth and fifth diffusion regions and the first gate electrode strip 206a form a second transistor T2. The second and third diffusion regions and the second gate electrode strip 206b form a third transistor T3. The fifth and sixth diffusion regions and the second gate electrode strip 206b form a fourth transistor T4. The first through fourth transistors T1-T4 correspond to the first through fourth transistors 102a-102d, i.e., the first through fourth memory cells M1, M2, M3, and M4 of the ROM array 100, respectively.
The first metal strip 208a is connected to the first gate electrode strip 206a by way of the first contact 210a. The second metal strip 208b is connected to the second gate electrode strip 206b by way of the second contact 210b. The fifth metal strip 208e is connected to the second diffusion region by way of the third contact 210c. The sixth metal strip 208f is connected to the fifth diffusion region by way of the fourth contact 210d. The first and second metal strips 208a and 208b represent the first and second word lines 106a and 106b, respectively. The seventh and eighth metal strips 208g and 208h represent the first and second bit lines 104a and 104b, respectively. The third and fourth metal strips 208c and 208d represent the first and second ground lines 108a and 108b, respectively.
The first diffusion region is connected to the third metal strip 208c by way of the fifth contact 210e for storing the first data value in the first memory cell M1. The fourth diffusion region is connected to the third metal strip 208c by way of the sixth contact 210f for storing the second data value in the second memory cell M2. The third diffusion region is kept floating for storing the third data value in the third memory cell M3. The sixth diffusion region is connected to the fourth metal strip 208d by way of the seventh contact 210g for storing the fourth data value in the fourth memory cell M4. This technique of storing the first through fourth data values is referred to as contact programming.
In operation, to read the first data value stored in the first memory cell M1, a pre-charging unit (not shown) pre-charges the first bit line 104a to a first voltage level for a predefined time interval. Thereafter, an address decoder (not shown) activates the first word line 106a for a predefined time interval, which switches on the first transistor 102a. Since the first diffusion terminal of the first transistor 102a is connected to the first ground line 108a and the second diffusion terminal of the first transistor 102a is connected to the first bit line 104a, the first bit line 104a is discharged to ground by way of the first transistor 102a. Subsequently, a sensing unit (not shown) senses the first bit line 104a, detects a low voltage, and reads the first data value as logic zero. The read operation of the second through fourth memory cells M2-M4 is performed in a similar manner.
FIG. 3 is a schematic circuit diagram of another conventional ROM array 300. The ROM array 300 is a 2×2 ROM array and includes first through fourth transistors 302a-302d (collectively referred to as transistors 302), first and second bit lines 304a and 304b (collectively referred to as bit lines 304), first and second word lines 306a and 306b (collectively referred to as word lines 306), and a ground line 308. The first through fourth transistors 302a-302d form first through fourth memory cells M1, M2, M3, and M4, and store first through fourth data values, respectively.
Each transistor 302 has a gate terminal, and first and second diffusion terminals. The gate terminals of the first and second transistors 302a and 302b are connected to the first word line 306a and the gate terminals of the third and fourth transistors 302c and 302d are connected to the second word line 306b. The first diffusion terminals of the first and second transistors 302a and 302b are connected to the ground line 308, and the second diffusion terminals of the first and second transistors 302a and 302b are connected to the first and second bit lines 304a and 304b for storing the first and second data values in the first and second memory cells M1 and M2, respectively. The first diffusion terminal of the third transistor 302c is connected to the ground line 308 and the second diffusion terminal thereof is floating for storing the third data value in the third memory cell M3. The first diffusion terminal of the fourth transistor 302d is connected to the ground line 308 and the second diffusion terminal is connected to the second bit line 304b for storing the fourth data value in the fourth memory cell M4. The first and second diffusion terminals may be either source or drain terminals.
FIG. 4 is a schematic layout diagram of a conventional 2×2 ROM array 400, which represents the ROM array 300 of FIG. 3. The ROM array 400 includes first and second active regions 402a and 402b (collectively referred to as active regions 402) formed on a semiconductor substrate 404. First and second gate electrode strips 406a and 406b (collectively referred to as gate electrode strips 406) are formed over the active regions 402. First through eleventh metal strips 408a-408k (collectively referred to as metal strips 408) are formed over the active regions 402 and the gate electrode strips 406 by way of first through eighth contacts 410a-410h (collectively referred to as contacts 410), and first through fifth vias 412a-412e (collectively referred to as vias 412). The first through seventh metal strips 208a-208g are metal 1 metal strips and the eighth through eleventh metal strips 208h-208k are metal 2 metal strips. The first active region 402a includes first through third diffusion regions of which the first and third diffusion regions are drain regions and the second diffusion region is a source region. The second active region 402b includes fourth through sixth diffusion regions of which the fourth and sixth diffusion regions are drain regions and the fifth diffusion region is a source region. The gate electrode strips 406 are polysilicon strips.
The first and second diffusion regions and the first gate electrode strip 406a form a first transistor T1. The fourth and fifth diffusion regions and the first gate electrode strip 406a form a second transistor T2. The second and third diffusion regions and the second gate electrode strip 406b form a third transistor T3. The fifth and sixth diffusion regions and the second gate electrode strip 406b form a fourth transistor T4. The first through fourth transistors T1-T4 correspond to the first through fourth transistors 302a-302d, i.e., first through fourth memory cells M1, M2, M3, and M4 of the ROM array 300.
The tenth metal strip 408j is connected to the first gate electrode strip 406a by way of the first via 412a, the first metal strip 408a, and the first contact 410a. The eleventh metal strip 408k is connected to the second gate electrode strip 406b by way of the second via 412b, the second metal strip 408b and the second contact 410b. The third metal strip 408c is connected to the second and fifth diffusion regions by way of the fourth and seventh contacts 410d and 410g, respectively. The fourth metal strip 408d is connected to the first diffusion region by way of the third contact 410c. The fifth metal strip 408e is connected to the fourth diffusion region by way of the sixth contact 410f. The sixth metal strip 408f is connected to the third diffusion region by way of the fifth contact 410e. The seventh metal strip 408g is connected to the sixth diffusion region by way of the eighth contact 410h. The tenth and eleventh metal strips 408j and 408k represent the first and second word lines 306a and 306b, respectively. The eighth and ninth metal strips 408h and 408i represent the first and second bit lines 304a and 304b, respectively. The third metal strip 408c represents the ground line 308.
The fourth metal strip 408d is connected to the eighth metal strip 408h by way of the third via 412c for storing the first data value in the first memory cell M1. The fifth metal strip 408e is connected to the ninth metal strip 408i by way of the fourth via 412d for storing the second data value in the second memory cell M2. The sixth metal strip 408f is kept floating for storing the third data value in the third memory cell M3. The seventh metal strip 408g is connected to the ninth metal strip 408i by way of the fifth via 412e for storing the fourth data value in the fourth memory cell M4. This technique of storing the first through fourth data values is referred to as via programming.
In operation, to read the first data value stored in the first memory cell M1, a pre-charging unit (not shown) pre-charges the first bit line 304a to a first voltage level for a predefined time interval. Thereafter, an address decoder (not shown) activates the first word line 306a for a predefined time interval, which switches on the first transistor 302a. Since the second diffusion terminal of the first transistor 302a is connected to the first bit line 304a and the first diffusion terminal of the first transistor 302a is connected to the ground line 308, the first bit line 304a is discharged to ground by way of the first transistor 302a. Subsequently, a sensing unit (not shown) senses the first bit line 304a, detects a low voltage corresponding to logic zero and reads the first data value as logic zero. The read operation of the second through fourth memory cells M2-M4 is performed in a similar manner.
Over the years, the requirement of increased storage capacity in ROM arrays has escalated. With advancements in semiconductor fabrication processes, miniaturization of electronic components such as transistors has also increased. Since each transistor stores a single data value, generally, the storage capacity is increased by increasing the number of memory cells, i.e., by increasing the number of transistors. However, process variations such as variations in length or width of a transistor, doping and other device parameters increase with the miniaturization of the transistors. Process variations are inversely proportional to the width and length of the transistors, and directly proportional to the number of the transistors. Thus, a ROM array with more transistors with each transistor having a reduced width for improved storage capacity has high process variations. This increase in the process variations results in a reduced yield of the fabrication process. Further, there is a significant degradation in the performance of the ROM array because the process variations weaken the memory cell. Designers must take into account the weak memory cells for timing closure that results in increased access time of the ROM array. Further, it takes longer to fabricate ROM arrays by contact programming because the metal layers such as metal 1, metal 2, and so on, and via layers are fabricated after the data values to be stored in the ROM array are determined.
Therefore, it would be advantageous to have a ROM array that has increased storage density and improved read access time, reduced power consumption and that generally overcomes the aforementioned limitations of the conventional ROM arrays.